The SCAN – Secure Processor with Crypto-Biometric Capability

Date/Time:   Oct. 23, 12 noon at the Engineering Building, Wright State University.
Location:       Room 148,  Russ College of Engineering

All are welcome to attend, they are going to have pizza and soft drinks.

Secure computing is gaining importance in recent times as computing capability is increasingly becoming distributed and information is everywhere. Prevention of piracy and digital rights management has become very important. Information security is mandatory rather than an additional feature. Numerous software techniques have been proposed to provide certain level of copyright and intellectual property protection. Techniques like obfuscation attempts to transform the code into a form that is harder to reverse engineer. Tamper-proofing causes a program to malfunction when it detects that it has been modified. Software watermarking embeds copyright notice in the software code to allow the owners of the software to assert their intellectual property rights. The software techniques discourage software theft, can trace piracy, prove ownership, but cannot prevent copying itself. Thus, software based security firewalls and encryption is not completely safe from determined hackers. This necessitates the need for information security at the hardware level, where secure processors assume importance.

In this talk the SCAN-Secure Processor is presented as a possible solution to these important issues mentioned above. The SCAN-SP is a modified Sparc V8 processor architecture with a new instruction set to handle image compression, encryption, information hiding and biometric authentication. A SCAN based methodology for encryption and decryption of 32 bit instructions and data and a Local-Global graph based methodology for biometric authentication is presented. The modules to support the new instructions are synthesized in reconfigurable logic and the results of FPGA synthesis are presented. The ultimate goal of the presented work is the tradeoffs that exists between speed of execution and security of the processor. Designing a faster processor is not the goal of the presented work, rather exploring the architecture to provide security is of prime importance.
Dr. Nikolaos Bourbakis (IEEE Fellow) is an OBR Distinguished Professor of IT and the Director of the Assistive Technologies Research Center (ATRC) at Wright State University, OH. He pursues research in Applied AI, Machine Vision, Bioinformatics & Bioengineering, Assistive Technologies, Information Security, and Parallel- Distributed Processing funded by USA and European government and industry. He has published more than 330 articles in refereed International Journals, book-chapters and Conference Proceedings, and 10 books as an author, co-author or editor. He has graduated 17Ph.Ds and 37 Master students. He is the founder and the EIC of the International Journal on AI Tools, the Editor-in-Charge of a Research Series of Books in AI (WS Publisher), the Founder and General Chair of several International IEEE Computer Society Conferences, Symposia and Workshops, an Associate Editor in several IEEE and International Journals and a Guest Editor in 18 journals special issues. His research work has been internationally recognized and has won several prestigious awards. Some of them are: IBM Author recognition Award 1991, IEEE Computer Society Outstanding Contribution Award 1992, IEEE Outstanding Paper Award ATC 1994, IEEE Computer Society Technical Research Achievement Award 1998, IEEE ICTAI 10 years Research Contribution Award 1999, IEEE Symposium on BIBE Outstanding Leadership Award 2003, ASC Award for Assistive Technology 2005, University of Patras Degree of Recognition 2007.